SC1486 Datasheet, PDF (12/17 Pages) Semtech Corporation – Dual Synchronous Buck Pseudo Fixed Frequency DDR Power Supply Controller

SC1486
POWER MANAGEMENT
Application Information (Cont.)
Stability Considerations
Unstable operation shows up in two related but distinctly
different ways: double pulsing and fast-feedback loop
instability. Double-pulsing occurs due to noise on the
output or because the ESR is too low, causing not enough
voltage ramp in the output signal. This causes the error
amplifier to trigger prematurely after the 400ns minimum
off-time has expired. Double-pulsing will result in higher
ripple voltage at the output, but in most cases is harm-
less. However, in some cases double-pulsing can indi-
cate the presence of loop instability, which is caused by
insufficient ESR. One simple way to solve this problem is
to add some trace resistance in the high current output
path. A side effect of doing this is output voltage droop
with load. Another way to eliminate doubling-pulsing is to
add a 10pF capacitor across the upper feedback resis-
tor divider network. This is shown below in Figure 5, by
capacitor C4 in the schematic. This capacitance should
be left out until confirmation that double-pulsing exists.
Adding this capacitance will add a zero in the transfer
function and should eliminate the problem. It is best to
leave a spot on the PCB in case it is needed.
+5V
+VIN
SC1486 ESR Requirements
The constant on-time control used in the SC1486
regulates the ripple voltage at the output capacitor. This
signal consists of a term generated by the output ESR of
the capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging
during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For
most applications the minimum ESR ripple voltage is
dominated by PCB layout and the properties of SP or
POSCAP type output capacitors. For applications using
ceramic output capacitors the absolute minimum ESR
must be considered. Existing literature describing the ESR
requirements to prevent double pulsing does not
accurately predict the performance of constant on-time
controllers. A time domain model of the converter was
developed to generate equations for the minimum ESR
empirically. If the ESR is low enough the ripple voltage is
dominated by the charging of the output capacitor. This
ripple voltage lags the on-time due to the LC poles and
can cause double pulsing if the phase delay exceeds the
off-time of the converter. Refering to Figure 5, the
equation for the minimum ESR as a function of output
capacitance and switching frequency and duty cycle is;
BST
DH
LX
ILIM
VDDP
DL
PGND
14
13
12
11
10
9
8
D1
C2
R1
+
C1
Q1
L1
D2
Q2
+
C3
FBK
0.5V - 5.5V
R2
C4
10pF
R3
FIGURE 5
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
The best way for checking stability is to apply a zero to
full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of
ringing after the initial step is sign that the ESR should
be increased.
ESR
>

R2 + R3
R3

•




2
1
•
+
3
•

Fs
-
200000
Fs
π • Cout •Fs •(1 − D

)
2




Dropout Performance
The output voltage adjust range for continuous-
conduction operation is limited by the fixed 500nS
(maximum) minimum off-time one-shot. For best
dropout performance, use the slowest on-time setting
of 200KHz. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on and off times. The IC duty-factor limitation
is given by:
DUTY =
T ON(MIN)
TON(MIN) + TOFF(MAX)
Be sure to include inductor resistance and MOSFET
on-state voltage drops when performing worst-case
dropout duty-factor calculations.
Layout Guidelines (TBD)
 2002 Semtech Corp.
12
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