EDGE629 Datasheet, PDF (1/16 Pages) Semtech Corporation – 1 GHz Timing Deskew and Quad Fanout Element

TEST AND MEASUREMENT PRODUCTS
Description
Edge629
1 GHz Timing Deskew and Quad
Fanout Element
Featur es
The Edge629 is a monolithic timing delay and signal fanout • Fmax ≥ 1 GHz
solution manufactured in a high-performance bipolar pro- • Independent Falling Edge Adjust
cess. In Automatic Test Equipment (ATE) applications, the • Small Footprint (10 mm x 10 mm)
Edge629 buffers, distributes, and aligns timing signals • Excellent Timing Accuracy
across multiple channels (typically found inside Memory • Very Stable Timing Delays
Test Systems). It is also suitable for per pin deskew in • 5 ps Resolution
Logic Testers.
• ECL, CMOS Compatible Inputs
The Edge629 supports:
• Minimum pulse width = 330 ps with Falling
Edge Adjust disabled, 500 ps with Falling
Edge Adjust enabled
• Net usable delay span ≥ 4.0 ns
• Falling Edge Adjust ± 250 ps
• On Board DACs to generate 5 ps resolution
With a maximum operating frequency of 1 GHz, the
Edge629 is optimized for extremely high speed, high ac-
curacy testers, particularly those aimed to test memory
devices.
Functional Block Diagram
The Edge629 solves several difficult problems associated
with aligning multiple timing signals because it can:
• delay very narrow pulses over a long
timing span
• adjust the falling edge independently from the overall
propagation delay
• maintain extreme timing accuracy for very narrow
(sub-ns) pulses
• maintain tight timing accuracy over changes in
frequency, duty cycle, and pattern.
IN0 / IN0*
IN / IN*
IN1/ IN1*
∆T–
∆T
∆T
Coarse
Fine
∆T–
∆T
∆T
Coarse
Fine
OUT0 / OUT0*
OUT1 / OUT1*
Applications
• Memory Test Equipment
– Data Fanout
– Channel Deskew
• Logic Testers
– Per Pin Deskew
• Clock / Signal Fanout
IN2 / IN2*
IN3 / IN3*
SEL / SEL*
∆T–
∆T
∆T
Coarse
Fine
OUT2 / OUT2*
∆T–
∆T
∆T
Coarse
Fine
OUT3 / OUT3*
Revision 3 / August 1, 2005
1
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