SKHI61 Datasheet, PDF (5/8 Pages) Semikron International – Sixpack IGBT and MOSFET Driver

Configuration pins
The configuration pins serve to adjust the TOP/BOTTOM
interlocking time of all halfbridges. Due to the special pin
design the interlocking time can be adjusted by a simple
connection to the BSTD terminal (BSS potential) on the
PCB without requiring external components.
Pin
TDT1
TDT2
SEL
4µs
(factory set)
3 µs
2 µs
open
open
open
open
GND
open
GND
open
open
1 µs
GND
GND
open
no
inter-loc
k )⁺
X
X
GND
Table 3: Values for interlocking time adjustment „X“ = no
effect
)+ TOP and BOTcan be switched simultaneously!
II. Secondary side
We have provided for five terminals per input. Two of them
are required for driving the IGBT, one is for short-circuit
protection. The remaining two have been designed for
optional adjustment of the V_CE-threshold.
IGBT-driver signals
We have provided for one gate- and one emitter input pin
per power switch, i.e. there is one gate resistor for turn-on
and turn-off each. The earth connection of the driver is
directly connected to the IGBT's emitter via the emitter
input, whereas a resistor of at least 10 Ω has to be
connected to the gate circuit. This resistance is the
minimum limit value controlled by the driver output buffer
in order to limit the pulse currents to their peak value.
A 20 kΩ-resistor has been interconnected between gate
and emitter (for the case that the supply voltage breaks
down).
C_VCE[nF]
=
t--_{b---l--a--n---k---}[_--µ_----s---]_---⋅_---(_{---7---2---,-7---5-----+----R-----V---C----E---}[_---k---Ω_-----]_---) _{– 0,1}
(R_VCE[ kΩ] + 4,75 ) ⋅ 36,08
R_VCE[kΩ]
=
------------1---1---^,---8---6------------- – 4,75
5, 4 – 0,93 V_CE
Equation 1
Equation 2
The V_CE-threshold cannot be increased, so that the preset
value of 5,8 V is the maximum value.
V_CE-monitoring can also be suppressed by connecting the
collector pin V_CE of one driver to the belonging emitter pin
E and not to the collector of the power semiconductor.
5V
TOP
0V
5V
BOT
0V
5V
Error
t _dIO
0V
14,9V
t _TD
0V
TOP
-6,5V
Gate- Emitter
14,9V
0V ^BOT
Gate- Emitter
-6,5V
t pERRESET
t _dERR
Vce- ERROR
with Soft
Turn Off
tblank+0,3us tsoft turn off
t > t _TD
Fig. 3 Course diagram: TOP and BOT-inputs and signal
Error compared to TOP and
BOT-Gate-Emitter-signal (valid for all halfbridges).
Gate-Emitter-voltage min
OFF (neg.)
-10
ON
14,4
Temperature drift
12
Typ max
-6.5 -5
14,9 15,4
14
16
Unit
V
V
mV/K
Table 4: Gate-emitter-voltage at T_A = 25 °C
V_CE -threshold and V_CE -monitoring
V_CE-monitoring is done by connection of the driver
collector pin to the collector of the power semiconductor.
If the turn-off threshold for short-circuit protection is to be
reduced (standard 5,8 V), a resistor has to be connected
between the V_CET1-threshold#1 pin 2 and V_CET2-
threshold#2 pin 4 (see fig. 4; Value to be calculated by
equation 1). Please do not forget to adapt the blanking
time¹ accordingly.
This can be done by attaching a capacitor (value to be
calculated by equation 2) between V_CE-threshold (pin 2)
and earth (pin 3). The V_CE-threshold may be adjusted to a
minimum value of about 3 V (R_VCE = 0 Ω).
1. Blanking time: time between turn-on of the power
semiconductor and V_CE-registration
Fig. 4 Connection principle of a power switch with a
specifically adjusted V_CE-threshold
60 kHz
50 kHz
40 kHz
30 kHz
20 kHz
10 kHz
Ta = 85°C
Ta = 55°C
0 kHz
0,0 µC
0,1 µC
0,2 µC
0,3 µC
0,4 µC
0,5 µC 0,6 µC 0,7 µC
gate charge
0,8 µC
0,9 µC
1,0 µC
1,1 µC
1,2 µC
Fig. 5 Maximum rating for output gate charge per pulse
1926 Driver Electronic – PCB Drivers
23-02-2004 © by SEMIKRON