SKHI24 Datasheet, PDF (3/8 Pages) Semikron International – Hybrid Dual IGBT Driver

PIN array
Fig. 6 shows the pin arrays. The input side (primary side) comprises 10 inputs, forming the interface to the control circuit
(see fig.1).
The output side (secondary side) of the hybrid driver shows two symmetrical groups of pins with 5 outputs, each forming
the interface to the power module. All pins are designed for a grid of 2,54 mm in two rows.
Primary side PIN array
PIN No. Designation
P1
Shield
P2
V_IN2
P3
V_IN1
P4, P5,
P6, P7
free
P8
/ERROR
P9, P10 GND/0V
P11, P12 V_S
P13
TDT1
P14
TDT2
P15
SELECT
P16, P17,
P18, P19, free
P20
Explanation
internally connected to GND
switching signal input 2 (BOTTOM switch); positive 5V logic
switching signal input 1 (TOP switch); positive 5V logic
not wired
error output, low = error; open collector output; max 30V / 15mA
ground
+ 15V ± 4% voltage supply
signal input for digital adjustment of locking time; to be switched by
bridge to GND
signal input for digital adjustment of locking time; to be switched by
bridge to GND
signal input for inhibiting locking function; to be connected by bridge
to GND
not wired
ATTENTION: The contactor tracks of the digital input signals P13/ P14/ P15 must not be longer than 20 mm to avoid
interferences, if no bridges are connected.
Secondary side PIN array
PIN No. Designation Explanation
ST1
ST2
ST3
G_OFF1
G_ON1
E1
gate 1 R_OFF output (TOP switch)
gate 1 R_ON output (TOP switch)
emitter output IGBT 1 (TOP switch)
ST4
ST9
SB1
SB2
SB3
C_CE1
V_CE1
G_OFF2
G_ON2
E2
reference voltage adjustment with R_CE and C_CE (TOP switch)
collector output IGBT 1 (TOP switch)
gate 2 R_OFF output (BOTTOM switch)
gate 2 R_ON output (BOTTOM switch)
emitter output IGBT 2 (BOTTOM switch)
SB4
SB9
C_CE2
V_CE2
reference voltage adjustment with R_CE and C_CE (BOTTOM switch)
collector output IGBT 2 (BOTTOM switch)
ATTENTION: The connector leads to the power module should be as short as possible.
© by SEMIKRON 22-08-2003
Driver Electronic – PCB Drivers 1917