LC86F3448B Datasheet, PDF (8/21 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

Pin Description
Pin Description Table
LC86F3448B
Terminal
I/O
Function Description
VSS
XT1
XT2
VDD
RES
FILT
CVIN
VS
HS
R
G
B
BL
Port 0
P00 to P07
Port 1
P10 to P17
-
Negative power supply
I
Input terminal for crystal oscillator
O
Output terminal for crystal oscillator
-
Positive power supply
I
Reset terminal
O
Filter terminal for PLL
I
Video signal input terminal(LC863400 only)
I
Vertical synchronization signal input terminal
I
Horizontal synchronization signal input terminal
O
Red (R) output terminal of RGB image output
O
Green (G) output terminal of RGB image output
O
Blue (B) output terminal of RGB image output
O
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
I/O •8-bit input/output port,
Input/output can be specified in nibble unit
•Other functions
AD converter input port (P04 to P07)
I/O •8-bit input/output port
Input/output can be specified for each bit
(programmable pull-up resister provided)
•Other functions
P10 IIC0 data I/O
P11 IIC0 clock output
P12 IIC1 data I/O
P13 IIC1 clock output
P14 PWM1 output
P15 PWM2 output
P16 PWM3 output
P17 Timer1 (PWM) output (LC863500 only)
Option
Flash Memory Mode
(Parallel input/
output mode)
Input to set up mode
Input to set up mode
Address input A8
Address input A9
Address input A10
Address input A11
Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD
Output Format
CMOS/Nch-OD
Address input
A0 to A7
Data input/output
D0 to D7
Port 3
P30 to P33
Port 7
P70
P71 to P73
I/O •LC863400:3-bit input/output port(P30toP32)
LC863500: 4-bit input/output port(P30toP33)
Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)
I/O •4-bit input/output port
Input or output can be specified for each bit
P70: I/O with programmable pull-up resister
P71 to P73: CMOS output/input with programmable pull-up resister
•Other functions
P70 INT0 input/HOLD release input/
Nch-Tr. output for watchdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/Timer 0 event input
P73 INT3 input (noise rejection filter connected)/
Timer 0 event input
Interrupt receiver format, vector addresses
INT0
Rising
enable
Falling
enable
Rising/
Falling
disable
H level
enable
L level
enable
Vector
03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
Address input
A12 to A15
Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC.
Control signal WE
Control signal OE
Control signal CE
No.A0120-8/21