LC863528 Datasheet, PDF (8/17 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

Pin Description
Pin name
I/O
VSS
-
XT1
I
XT2
O
VDD
-
RES
I
FILT
O
VS
I
HS
I
R
O
G
O
B
O
BL
O
Port 0
I/O
P00 to P07
Port 1
I/O
P10 to P17
LC863548B/40B/32B/28B/24B/20B/16B
Function
Negative power supply
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Positive power supply
Reset terminal
Filter terminal for PLL
Vertical synchronization signal input terminal
Horizontal synchronization signal input terminal
Red (R) output terminal of RGB image output
Green (G) output terminal of RGB image output
Blue (B) output terminal of RGB image output
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
• 8-bit input/output port
Input/output can be specified in nibble unit
(If the N-ch open drain output is selected by option, the corresponding port data can be
read in output mode.)
• Other functions
AD converter input port (P04 to P07 : 4 channels)
• 8-bit input/output port
Input/output can be specified for each bit
(programmable pull-up resister provided)
• Other functions
P10 IIC0 data I/O
P11 IIC0 clock output
P12 IIC1 data I/O
P13 IIC1 clock output
P14 PWM1 output
P15 PWM2 output
P16 PWM3 output
P17 Timer 1 (PWM) output
Option
Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD
Output Format
CMOS/Nch-OD
Port 3
P30 to P33
Port 7
P70
P71 to P73
I/O
• 4-bit input/output port
Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)
I/O
• 4-bit input/output port
Input or output can be specified for each bit
P70 : I/O with programmable pull-up resister
P71 to P73 : CMOS output/input with programmable pull-up resister
• Other function
P70 INT0 input/HOLD release input/
Nch-Tr. Output for watchdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/Timer 0 event input
P73 INT3 input (noise rejection filter connected) /
Timer 0 event input
Interrupt receiver format, vector addresses
INT0
rising
enable
falling
enable
rising/
falling
disable
H level
enable
L level
enable
vector
03H
INT1
enable
enable
disable
enable
enable
0BH
INT2
enable
enable
enable
disable
disable
13H
INT3
enable
enable
enable
disable
disable
1BH
Note : A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC.
Continued on next page.
No.7936-8/17