LC78632RE Datasheet, PDF (8/9 Pages) Sanyo Semicon Device – Compact Disk Player DSP

LC78632RE
Pin Functions
Pin No.
Symbol
I/O
Function
1
VPDO
O Test output
2
PDO2
O Double-speed and quad-speed mode playback PLL charge pump output. Must be left open if unused.
3
PDO1
O Normal-speed mode playback PLL charge pump output
4
AV_SS
5
FR
Analog system ground. Must be connected to 0 V.
Built-in VCO frequency range setting resistor connection
6
AV_DD
7
ISET
Analog system power supply
PDO1 and PDO2 output current setting resistor connection
8
TAI
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
9
EFMO
O EFM signal output
10
V_SS
Digital system ground. Must be connected to 0 V.
11
EFMI
I
EFM signal input
12
TEST1
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
13
CLV⁺
O
Spindle servo control output. CLV⁺ outputs a high level for acceleration, and CLV^– outputs a high level for
14
CLV^–
O ^{deceleration.}
Rough servo/phase control automatic switching monitor output. A high-level output indicates rough servo, and a
15
V/P
O
low-level output indicates phase control.
16
TEST2
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
17
TEST3
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
18
P4
I/O I/O port
19
HFL
I
Track detection signal input. This is a Schmitt input.
20
TES
I
Tracking error signal input. This is a Schmitt input.
21
PCK
O
EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phase is locked in normal-speed mode
playback.
Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the
22
FSEQ
O
EFM signal matches the internally generated synchronization signal.
23
TOFF
O Tracking off output
24
TGL
O Tracking gain switching output. Increase the gain when this pin outputs a low level.
25
THLD
O Tracking hold output
26
TEST4
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
27
V_DD
Digital system power supply
28
JP⁺
O
Track jump output. JP⁺ outputs a high level both for acceleration during outward direction jumps and for
deceleration during inward direction jumps. JP^– outputs a high level both for acceleration during inward direction
29
JP^–
O jumps and for deceleration during outward direction jumps.
30
SLD⁺
O
31
SLD^–
Sled output. This pin can be set to 1 of 4 levels by commands sent from the system control microprocessor.
O
32
EMPH
O De-emphasis monitor. A high level indicates that a disk requiring de-emphasis is being played.
33
P5
I/O I/O port
34
LRCKO
O
LR clock output
35
DFLRO
O
Digital filter outputs
LR data output. The digital filter can be turned off with the DFOFF command.
36
DACKO
O
Bit clock output
37
CONT1
O Output port
38
P0/DFCK
I/O I/O port. DF bit clock input in antishock mode.
39
P1/DFIN
I/O I/O port. DF data input in antishock mode.
I/O port. Used as the de-emphasis filter on/off switching pin in antishock mode. The de-emphasis filter is turned
40
P2
I/O _{on when this pin is high.}
41
P3/DFLR
I/O I/O port output or digital filter LR clock input (when anti-shock mode)
42
LRSY
O
LR clock output
43
CK2
O
ROMXA pins
44
ROMXA
O
45
C2F
O
Bit clock output. The polarity can be inverted with the CK2CON command.
Interpolated data output. Data that has not been interpolated can be output by issuing
the ROMXA command.
C2 flag output
46
MUTEL
O
Left channel mute output
47
LV_DD
Left channel power supply
48
LCHP
O
One-bit D/A
Left channel P output
49
LCHN
O
converter pins
Left channel N output
50
LV_SS
Left channel ground. Must be connected to 0V.
Note: Of the general-purpose I/O ports, any unused input ports must be connected to 0 V, or set to be output ports.
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