LV4124W Datasheet, PDF (7/21 Pages) Sanyo Semicon Device – Single-chip LCD panel driver IC(Supports the ALP202 LCD panel)

LV4124W
AC Characteristics (4)
Parameter
[Filter Characteristics]
Bandpass filter attenuation
Trap attenuation
Symbol
Conditions
min
ATBPF
Input SIG5 (VL = 0 mV) to (A) and SIG1
(0 dB) to (B). Take the T53 chrominance
amplitude when the center frequency
(3.58 and 4.43 MHz) is input to be 0 dB,
and measure the T53 output attenuation
for he frequencies listed at the right.
NTSC 1.50 MHz
PAL 2.00 MHZ
NTSC 5.50 MHz
PAL 6.80 MHz
ATRAPN
ATRAPP
Input SIG7 (0 dB, 3.58 and 4.43 MHz) to (A)
and measure the T44 output with a spectrum
analyzer. Taking the T44 amplitude in Y/C
mode to be 0 dB, determine the attenuation in
composite input mode.
NTSC
PAL
Ratings
Unit
typ
max
–15
–10
dB
–15
–10
dB
–7
–2
dB
–8
–3
dB
–40
–30
dB
–40
–30
dB
Input SIG5 (VL = 150 mV) to (A) and SIG2 (0 dB, 3.58 MHz
+ 100 kHz) to (B). Take the T44 output 100 kHz component
R-Y and B-Y low-pass filter
DEMLPF am plitude at this time to be 0 dB, and determine the
0.7
0.9
1.1 MHz
frequency at which the output beat component is reduced by
3 dB when the SIG2 frequency is increased from 3.58 MHz.
[Sync Separator Circuit and TG System]
Input SIG5 (VL = 0 mV, VS = 143 mV, variable WS) to (A)
and verify synchronization with the T23 HD output.
Input synchronizing signal
amplitude sensitivity
WSSEP Determine the value of WS at the point synchronization with
the T23 HD output is lost when the SIG5 WS is gradually
2.0
µs
made narrower starting at 4.7 µs.
Sync separator circuit input
sensitivity
VSSEP
Input SIG5 (VL = 0 mV, WS = 4.7 µs, variable VS) to (A) and
verify synchronization with the T23 HD output. Determine the
value of VS at the point synchronization with the T23 HD
output is lost when the SIG5 VS is gradually reduced starting
at 143 mV.
40
60 mV
Sync separator circuit output
TDSYL
Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS = 143 mV) to (A)
and measure the delay time with respect to the T12 RPD
output. Here, TDSYL is the delay from the fall of the input
430
630
830
ns
delay
HSYNC signal to the fall of the T12 RPD output, and TDSYH
is the delay from the rise of the input HSYNC signal to the
TDSYH _{rise of the T12 RPD output.}
4.7
5.0
5.3
µs
Horizontal pull-in range
HPLLN
HPLLP
Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS =
143 mV, variable horizontal frequency) to (A)
and verify synchronization withthe T23 HD
output. Determine the frequency fH at which
synchronization is achieved when the SIG5
horizontal frequency is varied starting from the
state where I/O synchronization is lost.
Calculate HPLLN = fH – 15734 and HPLLP =
fH – 15625.
NTSC
PAL
±500
±500
Hz
Hz
Continued on next page.
No.6000-7/21