LV4149W Datasheet, PDF (5/26 Pages) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

Continued from preceding page.
Parameter
Black limiter Dcvoltage
White limiter Dcvoltage
[Sync. separation, TG]
Parameter
Input sync signal width
sensitivity
Sync separation input
sensitivity
Sync separation output delay
rate
Horizontal pull-in range
Symbol
DVBLIM
DVWLIM
Symbol
WSSEP
VSSEP
TDSY1
TDSY2
HPLLN
HPLLP
LV4149W
Conditions
Enter SIG4 (VL = 0mV) to (A) and adjust BLIM to
set the TP43 output to 3Vp-p. Measure the DC
voltage of TP40, Tp43, and TP45.
Enter SIG4 (VL = 350mV) into (A), measure the
DC voltage of TP40, TP43, and TP45, and
determine the difference from the above VOUT.
Conditions
Enter SIG4 (VL = 0mV, VS = 143mV, WS variable)
to (A) and confirm synchronization with the
TP15HD output. Narrow WS of SIG4 from 4.7μs
and determine WS at which synchronization
between the input and TP15HD output is lost.
Enter SIG4 (VL = 0mV, WS = 4.7μs, VS variable)
to (A) and confirm synchronization with the
TP15HD output. Reduce VS of SIG4 from 143mV
and determine VS at which synchronization
between the input and TP15HD output is lost.
Enter SIG4 (VL = 0mV, WS = 4.7μs, VS = 143mV)
into (A) and measure the delay amount from the
TP2RPD output. Assume that the period from fall
of input HSYNC to a front edge of RPD output is
TDSY1 and the period from rise of input HSYNC to
the rear edge of RPD output is TDSY2.
Enter SIG4 (VL = 0mV, WS = 4.7μs, and VS =
143mV, horizontal frequency variable) to (A) and
confirm synchronization with TP15HD output.
Determine the horizontal frequency fH of SIG4 and
calculate
HPLLN = fH-15734
HPLLP = fH-15625.
min
3.3
Ratings
typ
3.5
3.3
3.5
min
2.0
Ratings
typ
40
300
500
150
300
±500
±500
Unit
max
3.7
V
3.7
V
Unit
max
μs
60
mV
700
ns
550
ns
Hz
Hz
Package Dimensions
unit : mm (typ)
3281
9.0
7.0
48
33
49
32
64
1
0.4
(0.5)
17
16
0.18
0.125
SANYO : LQFP64(7X7)
No.8929-5/26