LV4149W Datasheet, PDF (20/26 Pages) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

(2) 3-wave serial format
LV4149W
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
When 16 clocks of "SCLK" are entered while "LOAD" is "L", "DATA" is taken at fall of "SCLK" and the
operation is completed at rise of "LOAD."
(Note) If "SCLK" is 15 clocks or less while "LOAD" is "L", "DATA" is not taken. If "SCLK" is 17 clocks or
more, "DATA" up to 16 clocks is taken and "DATA" beyond 16 clocks is not taken.
(3) Data output timing
1. Various mode settings
Some items (with a circle in the V latch column of data specification) have data set at fall of the vertical
synchronous signal and some (without a mark in the V latch column) do not.
When data immediately before the vertical synchronous signal is transferred for multiple times, data immediately
before vertical synchronous signal becomes effective for items to be set with the vertical synchronous signal. For
items for whcih no setting is made, data becomes effective each time "DATA" is loaded.
2. Setting of the electric volume
D/A output data is changed at the same time with loading of "DATA."
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