LC89978M Datasheet, PDF (5/7 Pages) Sanyo Semicon Device – CCD Delay Line for Multi-System

LC89978M
Test Conditions
1. The supply current with no input signal
2. The pin output voltage (the center bias voltage) with no input signal
3. Measure the C-OUT output when a 350-mVp-p sine wave is input to C-IN1 and C-IN2.
C-OUT output [mVp-p]
G_VC = 20log
——————————
350 [mVp-p]
[dB]
Test frequencies:
G_VC-1: 4.431395 MHz (PAL/GBI)
G_VC-2: 3.571628 MHz (PAL/M)
G_VC-3: 3.571628 MHz (NTSC/M)
4. Measure the comb depth from the C-OUT output when a 350-mVp-p sine wave with frequency fa is input to C-IN1
and C-IN2, and when a sine wave of frequency fb is input.
The C-OUT output for an fb input [mVp-p]
C_D
=
20log
——————————————————
The C-OUT output for an fa input [mVp-p]
[dB]
Test Frequencies
fa
fb
C_D-1: 4.431395 MHz (PAL/GBI)
G_D-2: 3.571628 MHz (PAL/M)
G_D-3: 3.571628 MHz (NTSC/M)
4.435303 (PAL/GBI)
3.575561 (PAL/M)
3.563761 (NTSC/M)
5. Measure the C-OUT output when a 200-mVp-p sine wave is input to C-IN1 and C-IN2, and when a 500-mVp-p sine
wave is input, and calculate the gain difference as follows:
( ^{The output for a 500-mVp-p input [mVp-p]}
L_NC = 20log
——————————————————
500 [mVp-p]
Test Frequencies
L_NC-1
L_NC-2
L_NC-3
4.431395MHz (PAL/GBI)
3.571628MHz (PAL/M)
3.571628MHz (NTSC/M)
) ^{The output for a 200-mVp-p input [mVp-p]}
—————————————————— [dB]
200 [mVp-p]
6. Measure the 4fsc (14.3 MHz) and fsc (3.58 MHz) components in the C-OUT output with no input signal.
7. Measure the noise in the C-OUT output with no input signal.
Measure the noise with a noise meter with a 200-kHz high-pass filter and a 5-MHz low-pass filter.
8. Input a 350-mVp-p sine wave to C-IN1 and C-IN2. Let V1 be the C-OUT output when SW3 is set to the ‘a’ position,
and let V2 be the C-OUT output when SW3 is set to the 'b' position.
V2 [mVp-p] – V1 [mVp-p]
Z_OC =
——————————— × 500 [dB]
V1 [mVp-p]
Test Frequencies
Z_OC-1: 4.431395 MHz (PAL/GBI)
Z_OC-2: 3.571628 MHz (PAL/M)
Z_OC-3: 3.571628 MHz (NTSC/M)
9. The delay time in the C-OUT output with respect to the C-IN1 input. This is the CCD 1.5-bit delay.
10. The pin output voltage (clamp voltage) with no input signal.
No. 5546-5/7