LC89978M Datasheet, PDF (3/7 Pages) Sanyo Semicon Device – CCD Delay Line for Multi-System

LC89978M
Control Pin Functions
CONT1
Low
Low
High
High
CONT2
Low
High
Low
High
Mode (representative)
PAL/GBI
PAL/M
—
NTSC/M
Chrominance signal delay (number of CCD stages)
2H (1833.5) + 0H (1.5)
2H (1821.5) + 0H (1.5)
—
1H (911.5) + 0H (1.5)
Luminance signal delay (number of CCD stages)
1H (913)
1H (907)
—
1H (907)
Switching Voltage Levels
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Switching voltage level: low
V_L
Switching voltage level: high
V_H
–0.3
0.0
+0.5
V
2.0
5.0
6.0
V
Note: *Since the control pins have built-in pull-down resistors (about 70 kΩ), leaving these pins opens effectively sets them to the low level.
Function of the 4FSC Pin
This pin provides a 4fsc clock signal generated by the 4 × PLL frequency multiplier circuit.
Electrical Characteristics at V_DD = 5.0 V, Ta = 25°C, F_CLK = 3.579545 MHz, V_CLK = 500 mVp-p
Parameter
Symbol
I_DD-1
Supply current
I_DD-2
I_DD-3
[Chrominance signal characteristics] (with no input to Y-IN)
DC output voltage
Voltage gain
Comb depth
Linearity
Clock leakage (4fsc)
Clock leakage (fsc)
V_INC-1
V_INC-2
V_INC-3
V_OUTC-1
V_OUTC-2
V_OUTC-3
G_VC-1
G_VC-2
G_VC-3
C_D-1
C_D-2
C_D-3
L_NC-1
L_NC-2
L_NC-3
L_CK4C-1
L_CK4C-2
L_CK4C-3
L_CK1C-1
L_CK1C-2
L_CK1C-3
SW1
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
SW2
a
b
b
a
b
b
a
b
b
a
b
b
a
b
b
a
b
b
a
b
b
a
b
b
Switch states
SW3 SW4 Test conditions
a
b
*1
a
b
*1
a
b
*1
a
b
*2
a
b
*2
a
b
*2
a
b
*2
a
b
*2
a
b
*2
a
b
*3
a
b
*3
a
b
*3
a
b
*4
a
b
*4
a
b
*4
a
b
*5
a
b
*5
a
b
*5
a
b
*6
a
b
*6
a
b
*6
a
b
*6
a
b
*6
a
b
*6
Ratings
Unit
min
typ
max
31
36
41 mA
1.9
2.4
2.9
V
1.4
1.9
2.4
V
–2
0
+2
dB
–40
–35
dB
–0.3
0.0
+0.3
dB
10
50 mVrms
0.5
1.5 mVrms
Continued on next page.
No. 5546-3/7