LC87F2C64A Datasheet, PDF (4/28 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

LC87F2C64A
„Interrupts
• 28 sources, 10 vector addresses
(1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
(2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/INT4/T0L
4
0001BH
H or L
INT3/INT5/Base timer0/ Base timer1/RTC
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO1/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, 5/SPI
10
0004BH
H or L
Port0/T4/T5/PWM0, 1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
(1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the table above).
„Subroutine Stack Levels
• 1024 levels (Stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16 bits×8 bits
(5 tCYC execution time)
• 24 bits×16 bits
(12 tCYC execution time)
• 16 bits÷8 bits
(8 tCYC execution time)
• 24 bits÷16 bits
(12 tCYC execution time)
„Oscillation Circuits
• On-chip fast RC oscillation circuit
: For system clock
• On-chip slow RC oscillation circuit
: For system clock
• CF oscillation circuit
: For system clock, with built in Rf
• Crystal oscillation circuit
: For low-speed system clock
• On-chip Frequency variable RC oscillation circuit : For system clock
(1) Adjustable by ±4% (typical) step from selected center frequency
(2) Frequency measurable by referencing input signal from XT1
„System Clock Divider Function
• Enables low power consumption operation
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and 64μs
(at a main clock rate of 12MHz).
„Internal Reset Function
• Power-on reset (POR) function
(1) POR reset is generated only at power-on.
(2) The POR release level can be selected through option configuration.
• Low-voltage detection reset (LVD) function
(1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
(2) The use/no-use of the LVD function and the low voltage threshold level can be selected through option
configuration.
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