LV25200M Datasheet, PDF (37/45 Pages) Sanyo Semicon Device – Bi-CMOS IC Single chip Tuner IC for Car Radio

Continued from preceding page.
No.
Control block/data
(16) General-purpose counter
Control data
GT0, GT1
CTP
(17) DO pin control data
ULD
DT0, DT1
(18) Unlock detection data
UL0, UL1
(19) IF count operation control
data
CTS
(20) Sub-charge pump control
data
PDC0, PDC1
LV25200M
Description
¤ Data to determine the general-purpose counter measurement time
(frequency mode) and number of cycles (cycle mode).
Frequency measurement
GT1 GT0 _Measurement
Wait time
time
CTP=0
CTP=1
Cycle measurement
mode
0
0
4ms
3 to 4ms 1 to 2ms
1 cycle
0
1
8ms
3 to 4ms 1 to 2ms
1 cycle
1
0
32ms
7 to 8ms 1 to 2ms
2 cycles
1
1
64ms
7 to 8ms 1 to 2ms
2 cycles
¤ CTP=0: General-purpose counter input stopped at counter reset (CTE=0)
=1: General-purpose counter input not stopped and the wait time shortened at
counter reset (CTE=0)
Except that Immediately after setting of CTP=1, it is necessary to wait for counter start
till the general-purpose counter input pin is biased.
¤ Data to determine the output of DO pin.
ULD
DT1
DT0
DO pin
0
0
0
Low when unlocked
0
0
1
Do not use
0
1
0
end-UC
0
1
1
IN (*1)
1
0
0
Open
1
0
1
Do not use
1
1
0
end-UC
1
1
1
IN (*1)
end-UC: Count over of the general-purpose counter
Related data
DO
Start
End
(I-1 change)
CE:Hi
¤ Data to select the phase error (φE) detection width in order to check PLL for locking.
Phase error exceeding the φE detection width shown in the table below is determined to
indicate unlock. At unlock, the detection pin (DO) becomes Low.
UL1
UL0
φE detection width
Detection pin output
0
0
Stop
Open
0
1
0
φE output directly
1
0
±0.5μs
φE extended by 1 to 2ms
1
1
±1μs
φE extended by 1 to 2ms
ULD
DT0, DT1
φE
Extension
DO
1 to 2ms
Unlock output
¤ Data to select the general-purpose counter input pin (HCTR) in IC
CTS=1: HSTR pin in IC selected
0: HCTR pin in IC pulled down
¤ Data to control the sub-charge pump
PDC1
PDC0
Sub-charge pump state
UL0, UL1,
DLC
0
*
High impedance
1
0
Charge pump operating (unlocked)
1
1
Charge pump operating (normal)
(*: don’t care)
* The sub-charge pump output is connected internally with the LPF FET gate.
The sub-charge pump and the PD (main charge pump) pin are combined to form the fast
lockup circuit.
* Except that this may not be effective depending on the filter multiplier (lighter filter).
Continued on next page.
No.A0976-37/45