LC872G08A_10 Datasheet, PDF (22/27 Pages) Sanyo Semicon Device – 8K/6K/4K-byte ROM and 256-byte RAM integrated 8-bit 1-chip Microcontroller

LC872G08A/06A/04A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
„MURATA
Nominal
Frequency
Type
Oscillator Name
Circuit Constant
C1 C2
Rf
Rd
[pF] [pF] [Ω]
[Ω]
Operating
Voltage
Range
[V]
Oscillation
Stabilization Time
typ
max
[ms]
[ms]
Open 680
2.7 to 5.5
0.1
0.5
12MHz
SMD
CSTCE12M0G52-R0
(10) (10)
Open 1.0k
2.9 to 5.5
0.1
0.5
Open 680
2.2 to 5.5
0.1
0.5
SMD
CSTCE10M0G52-R0
(10) (10)
Open 1.0k
2.3 to 5.5
0.1
0.5
10MHz
Open 680
2.4 to 5.5
0.1
0.5
LEAD
CSTLS10M0G53-B0
(15) (15)
Open 1.0k
2.7 to 5.5
0.1
0.5
8MHz
Open 1.0k
2.2 to 5.5
0.1
0.5
SMD
CSTCE8M00G52-R0
(10) (10)
Open 1.5k
2.2 to 5.5
0.1
0.5
Open 1.0k
2.2 to 5.5
0.1
0.5
LEAD
CSTLS8M00G53-B0
(15) (15)
Open 1.5k
2.5 to 5.5
0.1
0.5
6MHz
Open 1.5k
2.2 to 5.5
0.1
0.5
SMD
CSTCR6M00G53-R0
(15) (15)
Open 2.2k
2.2 to 5.5
0.1
0.5
Open 1.5k
2.2 to 5.5
0.1
0.5
LEAD
CSTLS6M00G53-B0
(15) (15)
Open 2.2k
2.2 to 5.5
0.1
0.5
4MHz
Open 1.5k
1.8 to 5.5
0.2
0.6
SMD
CSTCR4M00G53-R0
(15) (15)
Open 3.3k
2.0 to 5.5
0.2
0.6
Open 1.5k
1.9 to 5.5
0.2
0.6
LEAD
CSTLS4M00G53-B0
(15) (15)
Open 3.3k
2.0 to 5.5
0.2
0.6
Remarks
Internal C1,C2
• CF oscillation low amplifier size selected (CFLAMP=1)
„MURATA
Nominal
Frequency
Type
Oscillator Name
Circuit Constant
C1 C2
Rf
Rd
[pF] [pF] [Ω]
[Ω]
Operating
Voltage
Range
[V]
Oscillation
Stabilization Time
typ
max
[ms]
[ms]
Remarks
4MHz
Open 1.0k
2.2 to 5.5
0.2
CSTCR4M00G53-R0
(15) (15)
Open 2.2k
2.3 to 5.5
0.2
SMD
Open 1.0k
2.2 to 5.5
0.2
CSTCR4M00G53095-R0 (15) (15)
Open 2.2k
2.2 to 5.5
0.2
Open 1.0k
2.2 to 5.5
0.2
CSTLS4M00G53-B0
(15) (15)
Open 2.2k
2.3 to 5.5
0.2
LEAD
Open 1.0k
2.2 to 5.5
0.2
CSTLS4M00G53095-B0 (15) (15)
Open 2.2k
2.2 to 5.5
0.2
0.6
0.6
0.6
0.6
Internal C1,C2
0.6
0.6
0.6
0.6
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than
minimum operating voltage. (See Fig. 3)
• Time till the oscillation gets stabilized after the CPU reset state is released
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset.
• Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0
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