LC87F7932B Datasheet, PDF (17/29 Pages) Sanyo Semicon Device – 32K-byte FROM and 2048-byte RAM integrated 8-bit 1-chip Microcontroller

LC87F7932B
Allowable Operating Conditions at Ta=-40 to +85°C, VSS1=VSS2=0V
Parameter
Symbol
Operating
supply voltage
VDD(1)
Pin/Remarks
VDD1=VDD2=V2
Conditions
0.75μs≤tCYC≤200μs
Normal mode
VDD[V]
Specification
min
typ
max
unit
2.4
3.6
(Note 2-1)
Memory
sustaining
VHD
VDD1=VDD2=V2
RAM and register contents
sustained in HOLD mode.
2.2
3.6
supply voltage
High level
input voltage
VIH(1)
Port 0, 3
LPA, LPB, LPC, LPL
Output disabled
2.4 to 3.6
0.3VDD
+0.7
VDD
VIH(2)
Port 1
Port 71 to 73
P70 port input
• Output disabled
• When INT1VTSL=0
(P71 only)
2.4 to 3.6
0.3VDD
+0.7
VDD
/ interrupt side
VIH(3)
VIH(4)
P71 interrupt side
P70 watchdog timer
Side
• Output disabled
• When INT1VTSL=1
Output disabled
2.4 to 3.6 0.85VDD
2.4 to 3.6 0.9VDD
VDD
V
VDD
Low level input
voltage
VIH(5)
VIL(1)
XT1, XT2, CF1, RES
Port 0, 3
LPA, LPB, LPC, LPL
Output disabled
2.4 to 3.6
2.4 to 3.6
0.75VDD
VSS
VDD
0.2VDD
VIL(2)
Port 1
Port 71 to 73
P70 port input
• Output disabled
• When INT1VTSL=0
(P71 only)
2.4 to 3.6
VSS
0.2VDD
/ interrupt side
VIL(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
2.4 to 3.6
VSS
0.45VDD
VIL(4)
P70 watchdog timer
side
2.4 to 3.6
VSS
0.8VDD
-1.0
Instruction
cycle time
VIL(5)
tCYC
XT1, XT2, CF1, RES
2.4 to 3.6
2.4 to 3.6
VSS
0.25VDD
200 μs
(Note 2-2)
External
FEXCF(1)
CF1
• CF2 pin open
system clock
• System clock frequency
frequency
division ratio = 1/1
2.4 to 3.6
0.1
4
• External system clock
duty = 50±5%
MHz
• CF2 pin open
• System clock frequency
2.4 to 3.6
0.2
8
division ratio = 1/2
Oscillation
frequency
FmCF(1)
CF1, CF2
• 4MHz ceramic oscillation
• See Fig. 1.
2.4 to 3.6
4
MHz
range
(Note 2-3)
FmRC(1)
FsRC(1)
FsX’tal
XT1, XT2
Internal Fast RC oscillation
Internal Slow RC oscillation
• 32.768kHz crystal
2.4 to 3.6
2.4 to 3.6
250
500
25
50
750
75
kHz
oscillation
2.4 to 3.6
32.768
• See Fig. 2.
Frequency
variable RC
oscillation
usable range
OpVMRC(1)
OpVMRC(2)
When VMSL4M=0
When VMSL4M=1
3.0 to 3.6
2.4 to 3.6
8
10
3.5
4
12
MHz
4.5
Frequency
variable RC
VmADJ(1)
Each step of VMRAJn
(Wide range)
2.4 to 3.6
8
24
64
oscillation
adjustment
range
VmADJ(2)
Each step of VMFAJn
(Small range)
2.4 to 3.6
1
4
%
8
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1841-17/29