LC72711W Datasheet, PDF (14/29 Pages) Sanyo Semicon Device – Mobile FM Multiplex Broadcast DARC Receiver IC

LC72711W, 72711LW
• BLK_RST
0: (default)
1: Resets the block synchronization circuit only.
Sets the block synchronization status to unsynchronized and clears the block synchronization protection counter.
However, note that this has no effect on the frame synchronization functions. Also note that during a
synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
• SUBBLK
0: Normal status. (default)
1: Set to 1 when a substation (for example a dGPS station during VICS reception) is temporarily received.
RD
DATn
Valid
output
RDY
timing 1
RDY
timing 2
Layer 4 CRC Register
RDY Signal Output Timing
Address Register R/W Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
06H
CRC4
W
00H
(LSB)
This is the data group write register used for the layer 4 CRC check. It is used only when the parallel interface is used.
Applications should specify the dedicated CCB address when using the serial interface.
Status Register
Address Register R/W Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
01H
STAT
R
—
VH
BLK
FRM
ERR
PRI
HEAD
CRC4
RTIB
• VH
0: Indicates data for which only horizontal correction was performed.
1: Indicates data for which after horizontal correction, vertical and then second horizontal correction were performed as
well.
Packet data with an RTIB flag is output with VH set to 0.
• BLK
0: Indicates data that was received with block synchronization unsynchronized.
1: Indicates data that was received with block synchronization synchronized.
• FRM
0: Indicates data that was received with frame synchronization unsynchronized.
1: Indicates data that was received with frame synchronization synchronized.
• ERR
0: Indicates data for which error correction completed and no errors were detected in the level 2 CRC check.
1: Indicates data for which error correction was not possible or for which errors were detected in the level 2 CRC
check.
• PRI
0: Indicates data that was inferred to be data block data by the frame synchronization circuit.
1: Indicates data that was inferred to be parity block data by the frame synchronization circuit.
Packet data with an RTIB flag is output with PRI set to 0.
No. 6167-14/29