LC89051V Datasheet, PDF (13/15 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89051V
3. The following output settings can be controlled:
• Channel status (C bit) output
• Subcode Q data output
• Start ID and shortening ID detection for DAT with subcodes
C bit output
• This IC only handles the first 32 bits.
• The flag is fixed at the high level (only when CKSEL is high), and the data format is LSB first.
• Error and update checking is not applied to the data.
• The internal shift register is reset if a PLL lock error occurs.
• Since the channel status information consists of 192 frames, a fixed period must be provided between data readout
operations.
1
fs
×
192
(ms)
<
(the
interval
between
data
readout
operations)
Subcode Q output
• Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this
signal falls. However, this signal will not be output (fall) unless 96-bit subcode Q data (including the CRC check
bits) is input.
• The flag outputs a high when the CRC check passes, and low if the CRC check fails. Besides, the shift clock SCLK
is required to be input regardless of the CRC flag status after latch pulse input.
• The bit order is LSB first within each byte of the 80 bits of subcode Q data.
ID detection
• The start ID and shortening ID are only detected when the DAT category code (1100000L) is received.
• These IDs are detected as follows:
— A low pulse is output from DQSY/LD if a start ID (R₀) or a shortening ID (L₁) is detected following a sync
signal (L₀).
— After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for
subcode Q data to SWDT/DI.
Figure 4 User Data for DAT with Subcodes
• The table below shows the relationship between the sync signal (L₀), the start ID (R₀), the shortening ID (L₁), and
the data output.
(L₀): SYNC
(R₀): Start ID
(L₁): Shortening ID
Flags + 80 data bits
Detected ID
H
H
L
all H
Start ID
H
L
H
all L
Shortening ID
• Output pins
The output scheme used for SRDT/DO differs depending on the microcontroller interface format selected by
CKSEL
L
H
Format
Figure 2
Figure 3
SRDT/DO
High open-drain output
Three-state output
No. 5543-13/15