LC877424A Datasheet, PDF (13/22 Pages) Sanyo Semicon Device – 8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip

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Parameter
Symbol
Pin capacitance
CP
Input sensitivity
Vsen
LC877448A/40A/32A/24A
Pins
All pins
Port 87 small signal
input
Conditions
•All other terminals
connected to VSS.
•f=1MHz
•Ta=25°C
VDD [V]
min
2.5 to 6.0
2.5 to 6.0
0.12VD
D
typ
max
unit
10
pF
Vp-p
Serial Input / Output Characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
[Serial clock]
[Input clock]
Cycle time
tSCK1
SCK0(P12)
Refer to figure 6
4/3
Low level pulse
width
tSCKL1
tSCKLA1
2/3
2.5 to 6.0
2/3
High level pulse
tSCKH1
2/3
width
tSCKHA1
5
Cycle time
tSCK2
SCK1(P15)
Refer to figure 6
2
Low level pulse
width
High level pulse
width
tSCKL2
tSCKH2
2.5 to 6.0
1
1
[Output clock]
Cycle time
Low level pulse
width
tSCK3
tSCKL3
tSCKLA2
SCK0(P12)
•CMOS output
•Refer to figure 6
2.5 to 6.0
4/3
1/2
3/4
High level pulse
tSCKH3
1/2
width
tSCKHA2
2
Cycle time
Low level pulse
width
High level pulse
width
tSCK4
tSCKL4
tSCKH4
SCK1(P15)
•CMOS output
•Refer to figure 6
2.5 to 6.0
2
1/2
1/2
[Serial input]
Data set-up time
tsDI
Data hold time
thDI
[Serial output]
SI0(P11), SI1(P14),
•Measured with respect 4.5 to 6.0
0.03
SB0(P11), SB1(P14)
to SIOCLK leading
2.5 to 6.0
0.1
edge
4.5 to 6.0
0.03
•Refer to figure 6
2.5 to 6.0
0.1
Output delay time
tdDO
SO0(P10), SO1(P13),
SB0(P11), SB1(P14)
•When port is open
drain: Time delay
from SIOCLK trailing
edge to the SO data
change
•Refer to figure 6
4.5 to 6.0
2.5 to 6.0
1/3tCY
C
+0.05
1/3tCY
C
+0.25
unit
tCYC
tCYC
tSCK
tCYC
tSCK
µs
µs
No.7776-13/22