LC895196 Datasheet, PDF (11/12 Pages) Sanyo Semicon Device – ATA-PI Compatible CD-ROM Decoder IC

LC895196
D7 to D0 (input/output)
This is the MC-side data bus. Built-in pull-up resistor.
ZINT (output)
This is the interrupt signal to the microcontroller.
3. The Buffer RAM
IO0 to IO15 (input/output)
This is the buffer DRAM data bus. Built-in pull-up resistors.
RA0 to RA9 (output)
These are the address pins for the buffer RAM.
ZRAS0 and ZRAS1 (output)
These are the RAS output pins for the buffer DRAM. Normally ZRAS0 is used; however, when two 1M (64K × 16
bit )DRAMS are used, connect the RAS pins of each DRAM to ZRAS0 and ZRAS1.
ZCAS0 and ZCAS1 (output)
This is the CAS output pin for the buffer DRAM. Normally ZCAS0 is used. When two 1M (64K × 16 bit) DRAMS
are used, connect the ZCAS0 output to the CAS pin of each DRAM. When the 2CAS types is used, connect ZCAS0
to UCAS and connect ZCAS1 to LCAS.
ZOE (output)
The read output signal for the buffer DRAM.
ZUWE, ZLWE (output)
This is the write output signal for the buffer DRAM. This connects to various DRAM pins. When the 2CAS type is
used, connect ZLWE to the write enable signal.
4. Subcode Interface
EXCK, WFCK, SBSO, SCOR (input or output)
These are the subcode interface pins. By connecting these to the CD-DSP the subcode data is accepted by the
LC895196 and transferred to the host.
5. The CD-DSP Data
BCK, SDATA, LRCK, C2PO (input)
When connected to CD-DSP, CD-ROM data is acquired. C2PO is a pin for use by the C2 flag.
6. The D/A Converter Interface
DLRCK, DBCK (output)
These are the DAC pins made by XTALCK0 or XTALCK1.
DSDATA (output)
This outputs serial data to the DAC.
7. Other Pins
ZRESET (input)
This is the LC895196 reset pin. The LC895196 is reset when this signal is low. This signal must be kept low for at
least a period of 1 µs after power on.
XTALCK0, XTAL0
These cause oscillation at 25 MHz or 27 MHz. Multiples of these respective clocks may also be input. Frequencies
from the outside may also be input into XTALCK0.
XTALCK1, XTAL1
These are specialty pins for the DLRCK, DBCK, and IDE, which output to the DAC. They cause a 33.8688 MHz
oscillation. A frequency may be input into XTALCK1 from the outside.
MCK (output)
This outputs the XTALCK1 and XTALCK1/2 frequencies. The output can also be turned off.
No. 5737-11/12