LC863448B Datasheet, PDF (11/17 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

LC863448B/40B/32B/28B/24B/20B/16B
IIC Input/Output Conditions / Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Standard
min
max
High speed
unit
min
max
SCL Frequency
fSCL
0
100
0
400
kHz
BUS free time between stop to start
tBUF
4.7
-
1.3
-
µs
HOLD time of start, restart condition
tHD ; STA
4.0
-
0.6
-
µs
L time of SCL
tLOW
4.7
-
1.3
-
µs
H time of SCL
tHIGH
4.0
-
0.6
-
µs
Set-up time of restart condition
tSU ; STA
4.7
-
0.6
-
µs
HOLD time of SDA
tHD ; DAT
0
-
0
0.9
µs
Set-up time of SDA
tSU ; DAT
250
-
100
-
ns
Rising time of SDA, SCL
tR
-
1000
20 + 0.1Cb
300
ns
Falling time of SDA, SCL
tF
-
300
20 + 0.1Cb
300
ns
Set-up time of stop condition
tSU ; STO
4.0
-
0.6
-
µs
Refer to figure 8
Note : Cb : Total capacitance of all BUS (unit : pF)
Pulse Input Conditions / Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
High/low level pulse
width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
tPIH(6)
tPIL(6)
Rising/falling time
tTHL
tTLH
Pins
• INT0, INT1
• INT2/T0IN
INT3/T0IN
(1 tCYC is selected for
noise rejection clock.)
INT3/T0IN
(16 tCYC is selected for
noise rejection clock.)
INT3/T0IN
(64 tCYC is selected for
noise rejection clock.)
RES
HS, VS
HS
Conditions
• Interrupt acceptable
• Timer 0-countable
• Interrupt acceptable
• Timer 0-countable
• Interrupt acceptable
• Timer 0-countable
• Interrupt acceptable
• Timer 0-countable
Reset acceptable
• Display position
controllable (Note)
• The active edge of HS
and VS must be apart
at least 1 tCYC.
• Refer to figure 4.
Refer to figure 4.
VDD[V]
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
min
1
2
32
128
200
3
Limits
typ
max
unit
tCYC
µs
500 ns
AD Converter Characteristics / Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Conditions
Resolution
N
Absolute precision ET
(Note)
Conversion time
tCAD
Vref selection 1-bit conversion time = 2 × tCYC
to conversion
finish
Analog input
VAIN
AN4 to AN7
voltage range
Analog port
input current
IAINH
IAINL
VAIN = VDD
VAIN = VSS
Note : Absolute precision does not include quantizing error (1/2LSB).
VDD [V]
4.5 to 5.5
min
VSS
-1
Limits
typ
max
unit
6
bit
±1 LSB
1.69
µs
VDD
V
1
µA
No.7935-11/17