KBE00G003M Datasheet, PDF (9/89 Pages) Samsung semiconductor – NAND 512Mb*2 + Mobile SDRAM 256Mb*2

KBE00G003M-D411
Figure 1. Functional Block Diagram
VCC
VSS
A9 - A26
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
A8
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
CLE ALE WP
MCP MEMORY
1,024M + 32M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 262,144
Page Register & S/A
Y-Gating
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
I/0 0
Driver
I/0 7
Figure 2. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
256K Pages
(=8,192 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512B Bytes
16 Bytes
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 8,192 Blocks
= 1,056 Mbits
8 bit
Page Register
512 Bytes
I/O 0 ~ I/O 7
16 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10
A11
A12
A13
A14
A15
3rd Cycle A17
A18
A19
A20
A21
A22
A23
4th Cycle A25
A26
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
I/O 7
A7
A16
A24
*L
Column Address
Row Address
(Page Address)
9
Revision 0.1
July 2005