KBE00G003M Datasheet, PDF (64/89 Pages) Samsung semiconductor – NAND 512Mb*2 + Mobile SDRAM 256Mb*2

KBE00G003M-D411
MCP MEMORY
5. Write Interrupted by Precharge & DQM
1) tRDL = 2CLK
CLK
CMD
WR
*3
PRE
DQM
*2
DQ
D0 D1 D2
Masked by DQM
*NOTE:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pre-
charge of four banks operation.
6. Precharge
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
PRE
DQ
D0 D1 D2 D3
2) Normal Read (BL=4)
tRDL^*1
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
*2
PRE
Q0 Q1 Q2 Q3 ¹
Q0 Q1 Q2 Q3 ²
7. Auto Precharge
1) Normal Write (BL=4)
CLK
2) Normal Read (BL=4)
CLK
CMD
WR
ACT
CMD
RD
DQ
D0 D1 D2 D3
tRDL =2CLK
tDAL =tRDL + tRP^*4
DQ(CL2)
DQ(CL3)
Auto Precharge Starts@tRDL=2CLK ^*3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Auto Precharge Starts ^*3
*NOTE:
1. SAMSUNG can support tRDL=2CLK .
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP .
64
Revision 0.1
July 2005