K4S643232E- Datasheet, PDF (9/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V)

K4S643232E-TE/N
CMOS SDRAM
Parameter
Symbol
-50
Row active to row active delay
tRRD(min)
10
RAS to CAS delay
tRCD(min)
15
Row precharge time
tRP(min)
15
Row active time
tRAS(min)
40
tRAS(max)
Row cycle time
tRC(min)
55
Version
-60
12
18
18
42
100
60
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS Latency=3
tCC
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
tSAC
CAS Latency=2
Output data hold time
tOH
CLK high pulse width
CAS Latency=3
tCH
CAS Latency=2
CLK low
pulse width
CAS Latency=3
tCL
CAS Latency=2
Input setup time
CAS Latency=3
tSS
CAS Latency=2
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output
in Hi-Z
CAS Latency=3
tSHZ
CAS Latency=2
-50
Min Max
5
1000
10
-
4.5
-
6
2
-
2
-
3
-
2
-
3
-
1.5
-
2.5
-
1
-
1
-
-
4.5
-
6
-60
Min Max
6
1000
10
-
5.5
-
6
2
-
2.5
-
3
-
2.5
-
3
-
1.5
-
2.5
-
1
-
1
-
-
5.5
-
6
Unit
-70
14
ns
20
ns
20
ns
49
ns
us
70
ns
-70
Min Max
7
1000
10
-
5.5
-
6
2
-
3
-
3
-
3
-
3
-
1.75
-
2.5
-
1
-
1
-
-
5.5
-
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1, 2
2
3
3
3
3
2
-
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
-9-
Rev. 1.4 (Dec. 2001)