K4S643232E- Datasheet, PDF (7/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V)

K4S643232E-TE/N
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = -25^oC to +85^oC, VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Symbol
Test Condition
CAS
Speed
Latency
-50
-60
-70
Operating Current
(One Bank Active)
Burst Length =1
3
175
170
155
ICC1
tRC ≥ tRC(min), tCC ≥ tCC(min), Io =
0mA
2
150
150
150
Precharge Standby Current ^ICC2P
CKE ≤ VIL(max), tCC = 15ns
3
in power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
2
ICC2N
Precharge Standby Current
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
20
in non power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
Active Standby Current
ICC3P
CKE ≤ VIL(max), tCC = 15ns
7
in power-down mode
ICC3PS CKE ≤ VIL(max), tCC = ∞
5
Active Standby Current
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
55
in non power-down mode
(One Bank Active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
40
Operating Current
(Burst Mode)
ICC4
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
3
2
190
150
180
150
170
150
Refresh Current
ICC5
tRC ≥ tRC(min)
3
190
185
165
2
160
160
160
3
Self Refresh Current
ICC6
CKE ≤ 0.2V
450
Unit Note
mA 2
mA
mA
mA
mA
mA 2
mA 3
mA 4
uA 5
Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232E-E**
5. K4S643232E-N**
Rev. 1.4 (Dec. 2001)
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