K4S28323LF-F Datasheet, PDF (9/12 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

K4S28323LF - F(H)E/N/S/C/L/R
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn CS
Register
Refresh
Mode Register Set
H
Auto Refresh
H
Entry
Self
Refresh
Exit
L
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Burst Stop
H
Bank Selection
Precharge
H
All Banks
Clock Suspend or
Active Power Down
Entry
H
Exit
L
Precharge Power Down
Mode
Entry
H
Exit
L
DQM
H
No Operation Command
H
X
L
H
L
L
L
H
H
X
L
X
L
X
L
X
L
X
L
H
L
L
HX
H
L
L
H
H
L
H
X
L
RAS CAS
WE DQM BA0,1 A10/AP
A11,
A9 ~ A0
L
L
L
X
OP CODE
L
LHX
X
H HH
X
X XX
L
HH X
V
H
LHX
V
H
L
LX
V
H HL X
V
L HLX
X
X XX
X
V VV
X XXX
X XX
X
H HH
X XX
X
V VV
X
V
X XX
X
H HH
X
Row Address
L
Column
H
Address
(A0~A7)
L
Column
H
Address
(A0~A7)
X
L
X
H
X
X
X
X
Note
1, 2
3
3
3
3
4
4, 5
4
4, 5
6
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation,
it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
February 2004