K4S28323LF-F Datasheet, PDF (7/12 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

K4S28323LF - F(H)E/N/S/C/L/R
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-60
Row active to row active delay
tRRD(min)
12
RAS to CAS delay
tRCD(min)
18
Row precharge time
tRP(min)
18
Row active time
tRAS(min)
42
tRAS(max)
Row cycle time
tRC(min)
60
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
Last data in to new col. address delay tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid output data
CAS latency=3
Number of valid output data
CAS latency=2
-
Number of valid output data
CAS latency=1
Version
-75
-1H
15
19
19
19
19
19
45
50
100
64
69
2
tRDL + tRP
1
1
1
2
1
-
Unit
Note
-1L
19
ns
1
24
ns
1
24
ns
1
60
ns
1
us
84
ns
1
CLK
2
-
3
CLK
2
CLK
2
CLK
4
ea
5
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
February 2004