S5N8952X Datasheet, PDF (8/18 Pages) Samsung semiconductor – ADSL Transceiver for NIC

5. Pin Description
S5N8952X
ADSL Transceiver for NIC
Table 1: Pin Description of the S5N8952X
No
Name
178 RESET_N
168 XTAL_IN
169 XTAL_OUT
156 EXT_CLK
172 PLL_FILT
152 TEST_MODE_3
150 TEST_MODE_2
146 TEST_MODE_1
144 TEST_MODE_0
139 TEST_SCN_EN
93 TEST_IN
92 TEST_OUT
182 TX_SHOW
183 RX_SHOW
158 GP_OUT_1
157 GP_OUT_0
165 BT_MODE_1
164 BT_MODE_0
161 NTR
I/O
Description
I System master reset (Active low)
I
O
System master clock (17.664MHz)
I
External clock for test
(Float in normal mode)
O
PLL pump out
(A 320pF capacitor between the pin and GNDA)
I
Chip test mode
[0] Normal mode, [1-15] Test mode
I Scan enable (Set to ‘0’ in normal mode)
I Test input (Float in normal mode)
O Test output (Float in normal mode)
O
Tx showtime indicator
(Active high. Connect to LED)
O
Rx showtime indicator
(Active high. Connect to LED)
O
General purpose outputs
(Float if not needed)
Boot mode
I [0] Reset, [1] Boot from host
[2] Boot from JTAG, [3] Self-booting
B
ATM network timing reference (8KHz. Float if not
needed)
200 PCI_AD_31
201 PCI_AD_30
203 PCI_AD_29
204 PCI_AD_28
207 PCI_AD_27
208 PCI_AD_26
1 PCI_AD_25
2 PCI_AD_24
9 PCI_AD_23
10 PCI_AD_22
12 PCI_AD_21
13 PCI_AD_20
16 PCI_AD_19
17 PCI_AD_18
20 PCI_AD_17
21 PCI_AD_16
44 PCI_AD_15
47 PCI_AD_14
48 PCI_AD_13
B PCI address data [31:0]
8
Preliminary Information (Rev.2.0)