KM732V689A Datasheet, PDF (8/15 Pages) Samsung semiconductor – 64Kx32 Synchronous SRAM

KM732V689A
Output Load(A)
Dout
Z0=50Ω
PRELIMINARY
64Kx32 Synchronous SRAM
RL=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667Ω
353Ω / 1538Ω
5pF*
* Capacitive Load consists of all components of
the test environment.
Fig. 1
* Including Scope and Jig Capacitance
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
-67
MIN
MAX
-72
MIN
MAX
-10
MIN
MAX
UNIT
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tSS
tDS
tWS
tADVS
tCSS
tAH
tSH
tDH
tWH
tADVH
tCSH
tPDS
tPUS
6.7
-
7.2
-
10
-
ns
-
3.8
-
4.0
-
4.5
ns
-
3.8
-
4.0
-
4.5
ns
0
-
0
-
0
-
ns
1.5
-
1.5
-
1.5
-
ns
0
-
0
-
0
-
ns
-
3.8
-
4.0
-
4.5
ns
1.5
3.8
1.5
4.0
1.5
4.5
ns
2.4
-
2.8
-
2.8
-
ns
2.4
-
2.8
-
2.8
-
ns
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
ns
0.5
-
0.5
-
0.5
-
ns
0.5
-
0.5
-
0.5
-
ns
0.5
-
0.5
-
0.5
-
ns
0.5
-
0.5
-
0.5
-
ns
0.5
-
0.5
-
0.5
-
ns
0.5
-
0.5
-
0.5
-
ns
2
-
2
-
2
-
cycle
2
-
2
-
2
-
cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
-8-
December 1998
Rev 1.0