KM732V689A Datasheet, PDF (7/15 Pages) Samsung semiconductor – 64Kx32 Synchronous SRAM

KM732V689A
PRELIMINARY
64Kx32 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/−0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Input Leakage Current(except ZZ)
Output Leakage Current
Operating Current
IIL
VDD=Max ; VIN=VSS to VDD
-2
IOL
Output Disabled, VOUT=VSS to VDDQ
-2
Device Selected, IOUT=0mA,
ICC
ZZ≤VIL, All Inputs=VIL or VIH
Cycle Time≥tCYC min
-67
-
-72
-
-10
-
Standby Current
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
Device deselected, IOUT = 0mA,
ISB
ZZ≤VIL, f = Max,
All Inputs≤0.2V or≥VDD-0.2V
-67
-
-72
-
-10
-
ISB1
Device deselected, IOUT = 0mA, ZZ≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
-
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f = Max, All Inputs≤VIL or≥VIH
-
VOL
IOL = 8.0mA
-
VOH
IOH = -4.0mA
2.4
VOL
IOL = 1.0mA
-
VOH
IOH = -1.0mA
2.0
VIL
-0.5*
VIH
2.0
VIL
-0.3*
VIH
1.7
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
MAX
+2
+2
320
280
220
80
70
60
20
20
0.4
-
0.4
-
0.8
VDD+0.5**
0.7
VDD+0.5**
UNIT
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
1ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
-7-
December 1998
Rev 1.0