K7J643682M Datasheet, PDF (8/17 Pages) Samsung semiconductor – 72Mb M-die DDRII SRAM Specification

K7J643682M
K7J641882M
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K
LD
R/W
D
D(A0)
D(A1)
Q(A0)
Q
Q(A1)
Stopped
X
X
Previous state
Previous state
Previous state
Previous state
↑
H
X
X
X
High-Z
High-Z
↑
L
H
X
X
DOUT at C(t+1)
DOUT at C(t+2)
↑
L
L
Din at K(t+1)
Din at K(t+1)
High-Z
High-Z
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
OPERATION
Clock Stop
No Operation
Read
Write
WRITE TRUTH TABLE(x18)
K
K
BW0
BW1
↑
L
L
↑
L
L
↑
L
H
↑
L
H
↑
H
L
↑
H
L
↑
H
H
↑
H
H
OPERATION
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
BW0
BW1
BW2
BW3
↑
L
L
L
L
OPERATION
WRITE ALL BYTEs ( K↑ )
↑
L
L
L
L
↑
L
H
H
H
↑
L
H
H
H
↑
H
L
H
H
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
↑
H
L
H
H
↑
H
H
L
L
↑
H
H
L
L
↑
H
H
H
H
↑
H
H
H
H
WRITE BYTE 1 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
-8-
Aug. 2005
Rev 1.0