K7J643682M Datasheet, PDF (16/17 Pages) Samsung semiconductor – 72Mb M-die DDRII SRAM Specification

K7J643682M
K7J641882M
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Power Supply Voltage
VDD
1.7
Input High Level
VIH
1.3
Input Low Level
VIL
-0.3
Output High Voltage(IOH=-2mA)
VOH
1.4
Output Low Voltage(IOL=2mA)
VOL
VSS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
Symbol
VIH/VIL
TR/TF
Typ
Max
Unit
1.8
1.9
V
-
VDD+0.3
V
-
0.5
V
-
VDD
V
-
0.4
V
Min
Unit
1.3/0.5
V
1.0/1.0
ns
0.9
V
Note
Note
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
50
20
20
5
5
5
5
5
5
0
Max
-
-
-
-
-
-
-
-
-
10
Unit
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JTAG TIMING DIAGRAM
TCK
TMS
TDI
PI
(SRAM)
TDO
tCHCH
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tSVCH
tCHSX
tCLQV
tCLCH
- 16 -
Aug. 2005
Rev 1.0