K4M563233E-M Datasheet, PDF (8/12 Pages) Samsung semiconductor – 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter
-75
Symbol
Min Max
-80
Min Max
-1H
Min Max
-1L
Unit Note
Min Max
CLK cycle time
CAS latency=3 tCC
7.5
8.0
9.5
9.5
CLK cycle time
CAS latency=2 tCC
9.5 1000 9.5 1000 9.5 1000 12 1000 ns 1
CLK cycle time
CAS latency=1 tCC
-
-
-
25
CLK to valid output delay CAS latency=3 tSAC
5.4
6
7
7
CLK to valid output delay CAS latency=2 tSAC
7
7
7
8 ns 1,2
CLK to valid output delay CAS latency=1 tSAC
-
-
-
20
Output data hold time
CAS latency=3 tOH
2.5
2.5
2.5
2.5
Output data hold time
CAS latency=2 tOH
2.5
2.5
2.5
2.5
ns 2
Output data hold time
CAS latency=1 tOH
-
-
-
2.5
CLK high pulse width
tCH
2.5
2.5
3.0
3.0
ns 3
CLK low pulse width
tCL
2.5
2.5
3.0
3.0
ns 3
Input setup time
tSS
2.0
2.0
2.5
2.5
ns 3
Input hold time
tSH
1.0
1.0
1.5
1.5
ns 3
CLK to output in Low-Z
tSLZ
1
1
1
1
ns 2
CAS latency=3
5.4
6
7
7
CLK to output in Hi-Z
CAS latency=2 tSHZ
7
7
7
8 ns
CAS latency=1
-
-
-
20
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
February 2004