DS_K6F8016U6C Datasheet, PDF (8/9 Pages) Samsung semiconductor – 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

K6F8016U6C Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
Address
tWC
tCW(2)
CS1
tAW
CS2
UB, LB
WE
tAS(3)
tBW
tWP(1)
Data in
tWR(4)
tDW
tDH
Data Valid
Preliminary
CMOS SRAM
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
2.7V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS1
GND
CS2 controlled
VCC
2.7V
CS2
VDR
0.4V
GND
CS1≥VCC - 0.2V
Data Retention Mode
tSDR
CS2≤0.2V
tRDR
8
Revision 0.0
May 2003