S6C0647 Datasheet, PDF (7/14 Pages) Samsung semiconductor – 256 CHANNEL TFT-LCD GATE DRIVER

256 CH. TFT-LCD GATE DRIVER
S6C0647
PIN DESCRIPTIONS
Symbol
Pin Name
I/O
Description
DI/O
DO/I
Start pulse input/output
When these inputs operate as the input, the start pulse data is
read at the rising edge of shift clock, CPV.
When these inputs operate as the output, the start pulse output
is the next chip’s start pulse input. The output pulse is
I/O
generated
at the falling edge of the 256th shift clock, CPV.
When U/D = H, the shift register does right shifting operation.
(Input = DI/O and output = DO/I)
When U/D = L, the shift register does left shifting operation.
(Input = DO/I and output = DI/O)
U/D
Shift direction control input
I
When U/D = H, DI/O → G001 →……→ G256 → DO/I
When U/D = L, DO/I → G256 →……→ G001 → DI/O
CPV
Shift clock input
I
The shift register operates in synchronization with the rising
edge of this input
OE1
OE2
OE3
Output enable input
These inputs control the state of the driver outputs.
I
When OE = H, the driver output is fixed to VSS2.
When OE = L, the driver output is VGG or VSS2 corresponding
to the data.
G001
to
G256
Driver output
The output signals change in synchronization with the rising
O edge of shift clock input, CPV.
The amplitude of the driver output is VGG - VSS2.
VSS2 Driver negative power supply
I
The input is internally connected to the logic ground, VSS1.
The input operates as the TFT panel gate OFF voltage.
VLO
Logic input low voltage
I Logic input range: VDD - VLO
VGG Driver positive power supply I The TFT gate ON voltage is VGG - VSS2.
VDD Logic positive power supply I 3.0 to 5.5 V
VSS1 Logic negative power supply
I
The logic negative power supply, VSS1, is internally connected
to the driver negative power supply, VSS2.
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