S6C0647 Datasheet, PDF (12/14 Pages) Samsung semiconductor – 256 CHANNEL TFT-LCD GATE DRIVER

S6C0647
256 CH. TFT-LCD GATE DRIVER
OPERATION DESCRIPTION
OPERATION METHOD
The start pulse input, DI/O (when U/D is “H”) or DO/I (when U/D = “L”), is synchronized with the rising edge of
CPV and stored in the first shift register.
While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored
simultaneously.
Output pin (G1 to G256) supplies VGG voltage or VSS2 voltage to the TFT-LCD panel depending on the pulse of
the shift register.
The start pulse output, DO/I (when U/D is “H”) or DI/O (when U/D = “L”), is synchronized with the falling edge of
CPV and the pulse of the last register (G1 or G256) is transferred to the next IC.
The voltage level of the start pulse output is VDD with “H” data, VSS1 with “L” data
The relationship between U/D and shift data inout pin is as follows:
Table 5. The relationship between U/D and the start pulse input / output
U/D Pin
“H” (VDD)
“L” (VSS1 - VLO)
Start pulse input / output
Input
Output
DI/O
DO/I
DO/I
DI/O
Data shift direction
G1 → G2 → G3 → G4 → G5 →……→ G256
G256 → G255 → G254 → G253 →……→ G1
OUTPUT PIN (G1 TO G256)
If the data of the shift register to an output drive pin is “H”, the voltage level of the output is VGG and if the data
is “L”, the level of the output is VSS2.
But, when OE is “H”, the voltage level of the output is VSS2 irrespective of the data of the shift register.
Condition
Pin
State
OE1
OE2
“H”
OE3
OE1
OE2
“L”
OE3
Table 6. The voltage level of the output
Control pin to LCD panel
Controlled output pin by OE signal
G1, G4, G7, …… , G250, G253, G256
G2, G5, G8, …… , G251, G254
G3, G6, G9, …… , G252, G255
G1, G4, G7, …… , G250, G253, G256
G2, G5, G8, …… , G251, G254
G3, G6, G9, …… , G252, G255
Output level
VSS2
Normal output
(VGG or VSS2)
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