K7S3236U4C Datasheet, PDF (7/20 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 QDR II+ b4 SRAM

K7S3236U4C
K7S3218U4C
1Mx36 & 2Mx18 QDR^TM II+ b4 SRAM
Depth Expansion
Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read
and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The allowable range of RQ is between 175Ω and 350Ω The value of RQ (within 15% tolerance) is five times the output impedance
desired. For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates
are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee
optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Output Valid Pin (QVLD)
The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing
the data. QVLD is edge aligned with CQ and CQ.
Echo clock operation
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-
chronized with internal data output. Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev. 1.0 August 2008
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