K7Q161882 Datasheet, PDF (7/17 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDR b2 SRAM

K7Q163682A
K7Q161882A
512Kx36 & 1Mx18 QDR^TM b2 SRAM
STATE DIAGRAM
POWER-UP
READ NOP
READ
WRITE
WRITE NOP
READ
WRITE
READ
LOAD NEW
READ ADDRESS
ALWAYS
(FIXED)
DDR READ
READ WRITE
LOAD NEW
WRITE ADDRESS
ALWAYS
(FIXED)
WRITE
WRIDTEDRPOWRRTITNEOP
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
-7-
July 2002
Rev 1.0