K6R4008C1D Datasheet, PDF (7/10 Pages) Samsung semiconductor – 512Kx8 Bit High Speed Static RAM(5.0V Operating)

K6R4008C1D
WRITE CYCLE*
Parameter
Symbol
Min
Write Cycle Time
tWC
10
Chip Select to End of Write
tCW
7
Address Set-up Time
tAS
0
Address Valid to End of Write
tAW
7
Write Pulse Width(OE High)
tWP
7
Write Pulse Width(OE Low)
tWP1
10
Write Recovery Time
tWR
0
Write to Output High-Z
tWHZ
0
Data to Write Time Overlap
tDW
5
Data Hold from Write Time
tDH
0
End of Write to Output Low-Z
tOW
3
* The above parameters are also guaranteed at industrial temperature range.
K6R4008C1D-10
PRELIMINARY
CMOS SRAM
Unit
Max
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
5
ns
-
ns
-
ns
-
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tRC
tOH
tAA
Previous Valid Data
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
tRC
tAA
tCO
tHZ(3,4,5)
OE
Data out
VCC
Current
tOHZ
tOE
High-Z
tOLZ
tLZ(4,5)
tDH
Valid Data
ICC
tPU
ISB
50%
tPD
50%
NOTES(WRITE CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-7-
Rev. 2.0
July 2004