K4S643232E Datasheet, PDF (7/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232E
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
ICC1
Burst Length =1
tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA
CAS
Latency _-45
Speed
-50 -55
-60
Unit Note
-70
3
180 175 175 170 155
mA 2
2
150 150 150 150 150
Precharge Standby Current in ^ICC2P
power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
ICC2N
ICC2NS
CKE ≤ VIL(max), tCC = 15ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
3
mA
2
20
mA
10
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P
ICC3PS
ICC3N
ICC3NS
CKE ≤ VIL(max), tCC = 15ns
CKE ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
7
mA
5
55
mA
40
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
ICC4
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
ICC5
tRC ≥ tRC(min)
ICC6
CKE ≤ 0.2V
3
200 190 190 180 170
mA 2
2
150 150 150 150 150
3
195 190 190 185 165
mA 3
2
160 160 160 160 160
3
mA 4
450
uA 5
Notes : _{1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.}
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232E-TC**
5. K4S643232E-TL**
Rev. 1.3 (Oct. 2001)
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