K4S643232E Datasheet, PDF (2/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232E
CMOS SDRAM
Revision History
Revision 1.3 (October 24, 2000)
• Removed CAS Latency 1 from the spec.
Revision 1.2 (August 7, 2000) - Target
• Added CAS Latency 1
Revision 1.1 (March 14, 2001)
• Added K4S643232E-55
Revision 1.0 (October 20, 2000)
• Removed Note 5 in page 9. tRDL is set to 2CLK in any case regardless of using AP or frequency
Revision 0.4 (August 24, 2000)
• Updated DC spec
Revision 0.3 (August 1, 2000)
• Changed the wording of tRDL related note for Users’ clear understanding
Revision 0.2 (July 18, 2000) - Preliminary
• Removed K4S643232E-40/55/7C
• Changed tSH of K4S643232E-45 from 0.7ns to 1.0ns
Revision 0.0 (March 14, 2000) - Target Spec.
• Initial draft
Rev. 1.3 (Oct. 2001)
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