K4S561632C Datasheet, PDF (7/11 Pages) Samsung semiconductor – 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM

K4S561632C
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
3.3V
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Z0 = 50Ω
Unit
V
V
ns
V
Vtt = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
Notes : 1. The DC/AC Test Output Load of K4S561632C-TC(L)60 is 30pF.
2. The VDD condition of K4S561632C-TC(L)60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Symbol
-60
tRRD(min) 12
tRCD(min) 18
tRP(min) 18
tRAS(min) 42
tRAS(max
tRC(min) 60
tRDL(min)
tDAL(min)
Version
-7C
-75
-1H
15
15
20
15
20
20
15
20
20
45
45
50
100
60
65
70
2
2 CLK + tRP
Unit Note
-1L
20
ns
1
20
ns
1
20
ns
1
50
ns
1
us
70
ns
1
CLK 2, 5
-
5
Last data in to new col. address delay tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Number of valid output
data
CAS latency=3
CAS latency=2
-
2
1
ea
4
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time}
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.4 Sept. 2001