K1S64161CC Datasheet, PDF (7/10 Pages) Samsung semiconductor – 4Mx16 bit Page Mode Uni-Transistor Random Access Memory

K1S64161CC
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)
Address
CS1
tCSHP
tRC
tAA
tCO
CS2
UB, LB
OE
Data out
High-Z
tBA
tOE
tOLZ
tBLZ
tLZ
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
A21~A2
Valid
Address
A1~A0
CS1
Valid
Address
tAA
tOH
Data Valid
tCHZ
tBHZ
tOHZ
Valid
Valid
Valid
Address Address Address
tPC
CS2
tCO
tHZ
OE
DQ15~DQ0
High Z
tPA
tOE
tOHZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
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Revision 1.0
April 2005