S6C1108 Datasheet, PDF (6/20 Pages) Samsung semiconductor – 6 BIT 384 CHANNEL RSDS TFT-LCD SOURCE DRIVER

S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
OPERATION DESCRIPTION
RSDS RECEIVER AND DEMUX
The S6C1108 adapts the RSDS interface for EMI solution. The internal RSDS receiver block operates the
comparison between the transmitted differential input pair data. The input data lines from the timing controller
to the RSDS receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs(DxxP/DxxN).
The input common mode voltage range at the RSDS receiver is 1.2V. The differential data and clock signals
from the panel timing controller arrive at the S6C1108 as multiplexed, even and odd data fields. (i.e., the data
is 2:1 multiplexed). The nominal peak to peak swing of this data is 200mV across a termination resistor.
RSDS DATA BUS INTERFACE CONTROL
DATPOL controls the internal data inversion. When DATPOL=”H”, the internal data is inverted. The inverted
data is the same that the RSDS receiver operates the comparison between the cross-transmitted differential
input pair data. Using the data inversion input pin, DATPOL, the RSDS data bus interface can be changed.
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into the internal latch on the falling edge of CLKP, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the 2nd falling edge of CLKP. Once all the
data of 384 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data
is not accepted even though CLKP is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is
provided, new display data is valid on the 2nd falling edge of CLKP after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
When SHL="L", Connect DIO1 pin of the previous stage to the DIO2 pin of the next stage and all the input
pins except DIO1 and DIO2 are connected together in each device.
When SHL="H", Connect DIO2 pin of the previous stage to the DIO1 pin of the next stage and all the input
pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 14 (7 by 2) gamma corrected power
supplies (VGMA1 to VGMA14). Besides, to be able to deal with dot line inversion when mounted on a single-
side, gradation voltages with different polarity can be output to the odd number output pins and the even
number output pins. Among 7-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity
with respect to the common voltage, for the respective 7 gamma corrected voltages of VGMA1 to VGMA7 and
VGMA8 to VGMA14.
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