KM416S1021C Datasheet, PDF (6/8 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

KM416S1021C
Preliminary
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS latency=3
CAS latency=2
CLK to Valid
Output Delay
CAS latency=3
CAS latency=2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-7
Min
Max
7
1000
12
5.5
7
2.5
3
3
2
1
1
5.5
7
-S
Min
Max
-
1000
10
-
6
2
3.5
3.5
2
1
1
-
8
-8
Min
Max
8
1000
13
6
8
2.5
3
3
2.5
1
1
6
8
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1,2
2
3
3
3
3
2
REV. 1. May '98