KM416S1021C Datasheet, PDF (1/8 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

KM416S1021C
Preliminary
CMOS SDRAM
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
FEATURES
• JEDEC standard 3.3V power supply
• SSTL_3 (Class II) compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The KM416S1021C is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part No.
Max Freq. Interface Package
KM416S1021CT-G7
KM416S1021CT-GS
KM416S1021CT-G8
143MHz
100MHz(CL=2)
125MHz
SSTL_3
(Class II)
54
TSOP(II)
* KM416S1021CT-GS : CL=2 only
Bank Select
Data Input Register
LWE
LDQM
512K x 16
CLK
ADD
512K x 16
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE L(U)DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
REV. 1. May '98