K7I163682B Datasheet, PDF (6/17 Pages) Samsung semiconductor – 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I163682B and K7I161882B will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I163682B and K7I161882B support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7I161882B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7I163682B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Clock Consideration
K7I163682B and K7I161882B utilize internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
K7I163682B and K7I161882B can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can′t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal
for each bank.
Before chip deselected, all read and write pending operations are completed.
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July. 2004
Rev 3.1