K4S561632D Datasheet, PDF (6/11 Pages) Samsung semiconductor – 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

K4S561632D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating current
(One bank active)
ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Precharge standby cur-
rent in power-down mode
Precharge standby cur-
rent in non power-down
mode
ICC2P
ICC2PS
ICC2N
CKE ≤ V IL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ V IH(min), CS ≥ VI H(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS ^{CKE ≥ V IH(min), CLK ≤ VIL(max), tCC = ∞}
Input signals are stable
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
CKE ≤ V IL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ V IH(min), CS ≥ VI H(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS ^{CKE ≥ V IH(min), CLK ≤ VIL(max), tCC = ∞}
Input signals are stable
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs
Refresh current
ICC5 tRC ≥ tRC(min)
C
Self refresh current
ICC6 CKE ≤ 0.2V
L
Version
Unit Note
-60 -7C -75 -1H -1L
150 110 100 100 100 mA 1
2
mA
2
20
mA
10
6
mA
6
30
mA
25
mA
180 140 140 130 130 mA 1
220 220 200 190 190 mA 2
3
mA 3
1.5
mA 4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632D-TC**
4. K4S561632D-TL**
5. Unless otherwise noticed, input swing level is CMOS(VI H/VIL=VDDQ /VSSQ ).
Rev. 0.1 Aug. 2002