K4S510732B Datasheet, PDF (6/11 Pages) Samsung semiconductor – Stacked 512Mbit SDRAM

K4S510732B
Preliminary
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
Version
Unit Note
-75 -1H -1L
135 125 125 mA 1
Precharge standby current in
power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
4
mA
4
Precharge standby current in
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
30
non power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
25
mA
Active Standby current
in power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
8
mA
8
Active standby current in
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
45
mA
non power-down mode
(One bank active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
40
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
IO = 0 mA
ICC4 ^{Page burst}
4banks activated.
tCCD = 2CLKs
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
170 145 145 mA 1
235 225 225 mA 2
C
6
mA 3
L
4
mA 4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510732B-TC**
4. K4S510732B-TL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 0.0 Feb.2001