K4S510732B Datasheet, PDF (3/11 Pages) Samsung semiconductor – Stacked 512Mbit SDRAM

K4S510732B
16M x 8Bit x 4 Banks Synchronous DRAM
Preliminary
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S510732B is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
Part No.
K4S510732B-TC/L75
K4S510732B-TC/L1H
K4S510732B-TC/L1L
Max Freq. Interface
133MHz(CL=3)
100MHz(CL=2) ^LVTTL
100MHz(CL=3)
Package
54pin
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
CLK,CAS,RAS
/WE,DQM
/CS1,CKE1
/CS0,CKE0
32Mx8
32Mx8
DQ0 ~ DQ7
A0~A12,BA0,BA1
* Samsung Electronics reserves the right to change products or specification without notice.
Stakteks’ stacking technology is Samsungs’ stacking technology of choice.
Rev. 0.0 Feb.2001